1. Filed of the Invention
The invention relates generally to semiconductor memory devices, and, more particularly, semiconductor memory devices with cache memories integrated on the same chip.
2. Description of the Background Art
A main memory contained in a computer system comprises a dynamic random access memory (hereinafter referred to as DRAM) of low speed and large capacity, therefore of low cost. In order to improve the cost performance of a computer system, a high speed memory of small capacity is often provided as a high speed buffer between a main memory and a central processing unit (hereinafter referred to as CPU). This high speed buffer is referred to as cache memory. In this cache memory, the blocks of data which CPU is most likely to require is copied and stored from the main memory. In the DRAM, the state in which the data stored in the address, which the CPU was to access to, also exists in the cache memory is called a "cache hit". In this case the CPU accesses a high speed cache memory, and reads out the required data from the cache memory. In the DRAM, the state in which the data stored in the address, which the CPU was to access to, does not exist in the cache memory is called a "cache miss". In this case, the CPU accesses a low speed main memory, and transfers the block, which the data belongs to, from the DRAM to the cache memory at the same time when it reads out the required data from the main memory.
However, such a cache memory system requires an expensive high speed memory, so that it can not be used in a small size computer system in which cost is valued highly. Therefore, conventionally, a simplified cash system was constituted, utilizing a page mode or a static column mode contained in a general purpose DRAM.
FIG. 10 is a block diagram showing a fundamental configuration of a conventional DRAM device capable of operating in a page mode or in a static column mode.
In FIG. 10, in a memory cell array 50, a plurality of word lines and a plurality of bit line pairs are arranged to intersect each other with a memory cell provided at each of their intersections. In FIG. 10, one word line WL, one bit line pair BL, BL, and one memory cell MC provided at the intersection of the word line WL and the bit line BL are only representatively shown.
The word line in the memory cell array 50 is connected to a row decoder 53 through a word driver 52. The bit line pair in the memory cell array is connected to a column decoder 56 through a sense amplifier portion 54 and an I/O switch 55. A row address buffer 57 and a column address buffer 58 are provided with multiplexed signals MPXA which are a row address signal RA and a column address signal CA multiplexed. The row address buffer 57 supplies the row address signal RA to the row decoder 53, and the column address buffer 53 supplies the column address signal CA to the column decoder 56. An output buffer 59 and an input buffer 60 are connected to the I/O switch 55.
FIGS. 11A, 11B and 11C respectively show operation waveform diagrams of a normal read cycle, a page mode cycle and a static column mode cycle of the DRAM device.
In the normal read cycle shown in FIG. 11A, the row address buffer 57 initially accepts the multiplexed address signal MPXA at the fall edge of a row address strove signal RAS, and supplies the same as a row address signal RA to the row decoder 53. The row decoder 53 selects one of a plurality of word lines in response to the row address signal RA. The selected word line is activated by the word driver 52. As a result, information stored in the plurality of memory cells connected to the word line is each read out on a corresponding bit line, and the information is detected and amplified by the sense amplifier portion 54. At this time, a row of information of the memory cell is latched in the sense amplifier portion 54.
Subsequently, the column address buffer 58 accepts a multiplexed address signal MPXA at the fall edge of a column address strobe signal CAS, and supplies the same as a column address signal CA to the column decoder 56. The column decoder 56 selects one bit out of one row of information latched in the sense amplifier portion 54 in response to the column address signal CA. This selected information is supplied to the outside as an output data Dout through the I/O switch 55 and the output buffer 59.
In this case, the access time (RAS access time) t.sub.RAC corresponds to the time period from the fall edge of the row address strobe signal RAS to the time when the output data Dout becomes valid. In this case, the cycle time t.sub.c is the sum of the time during which the device is in an active state and the RAS precharge time t.sub.RP. As a standard value, in the case in which t.sub.RAC =100 ns, t.sub.c is about 200 ns.
In the page mode cycle and the static column mode cycle shown in FIGS. 11B and 11C, a memory cell on the same row may be accessed by changing the column address signal CA. In the page mode cycle, the column address signal CA is latched at the fall edge of the column address strobe signal CAS. In the static column mode cycle, an access is made only by the change of the column address signal CA as in the static RAM (SRAM).
The CAS access time t.sub.CAC of the page mode cycle and the address access time t.sub.AA of the static column mode cycle attain a value of about 1/2 of the RAS access time t.sub.RAC, and when t.sub.RAC =100 ns, they are about 50 ns. In this case, the cycle time, which depends on the CAS precharge time t.sub.CP with regards to the page mode cycle, is shortened to be a value of about 50 ns, which is similar to the static column mode cycle.
FIG. 12 is a diagram showing a fundamental configuration of a 4M bit DRAM device of a conventional 1M .times.4 bits structure capable of operating in a page mode or in a static column mode.
In FIG. 12, the DRAM device 20 is formed on one chip. A memory cell array 1 is divided into 16 array blocks B1 to B16. As shown in FIG. 13, a sub memory cell array 101 comprises blocks B1, B5, B9, B13, and corresponds to an input and output data DQ1. Similarly, a sub memory cell array 102 corresponds to an input and output data DQ2, a sub memory cell array 103 corresponds to an input and output data DQ3, and a sub memory cell array 104 corresponds to an input and output data DQ4.
The address buffer 5 accepts externally applied address signals A0 to A9 at the fall edge of the row address strobe signal RAS supplied from an RAS buffer 6, and supplies the same as a row address signal RA to a row decoder 2. The row address signal RA comprises row address signals RA0 to RA9 of 10 bits. The address buffer accepts externally applied address signals A0 to A9 at the fall edge of the column address strobe signal CAS supplied from a CAS buffer 7, and supplies it as a column address signal CA to a column decoder 3. The column address signal CA comprises column address signals CA0 to CA9 of 10 bits. A sense control circuit 9 is responsive to row address signals RA8, RA9 of 2 bits among the row address signals RA to cause a sense amplifier portion 4 corresponding to four of the 16 array blocks B1 to B16 to operate.
A data output buffer 11 is responsive to an externally applied output enable signal OE to supply the information of 4 bits read out from the memory cell array 1 as output data DQ1 to DQ4 to the outside. A write buffer 10 is responsive to an externally applied write enable signal WE to supply a write signal W to a data input buffer 12. The data input buffer 12 is responsive to the write signal W to supply externally applied input data DQ1 to DQ4 of 4 bits to the memory cell array 1.
FIG. 14 is a block diagram fully showing the configuration of the sub memory cell array 101 corresponding to the input and output data DQ1. As shown in FIG. 14, the sub memory cell array 101 of 1M bits corresponding to one input and output bit is divided into four array blocks B1, B5, B9, B13 of 1K.times.256 bits respectively. Each array block is provided with a sense amplifier group 14 comprising a plurality of sense amplifiers, an I/O switch 17 and a column decoder 19. One of four array blocks B1, B5, B9, B13 is selectively driven in response to 2 bit row address signals RA8, RA9. In the configuration shown in FIG. 14, the number of sense amplifiers is increased, and the length of each bit line is shortened. As a result, the read voltage which is read out from the memory cell to the sense amplifier may be increased. In addition, by means of a dividing operation, it becomes possible to reduce power consumption.
In the array block selected by the row address signals RA8, RA9, one word line (not shown) is selected by the row decoder 2. The information stored in a plurality of memory cells (not shown) connected to the word line is supplied to the each corresponding sense amplifier through the each corresponding bit line (not shown). The information is sensed and amplified by the sense amplifiers.
In the example of FIG. 14, the sense amplifier group 14 corresponding to each array block comprises 1K (1024) sense amplifiers. In this case, one of four sense amplifier groups 14 provided corresponding to four array blocks B1, B5, B9, B13 is selectively driven in response to the row address signals RA8, RA9 of 2 bits. When the sense amplifier is activated, a row (1K.times.4 bits) of information is latched in the four sense amplifier groups 14. Accordingly, the page mode and the static column mode shown in FIGS. 11B and 11C are made possible by selecting a sense amplifier through the column decoder 19 by way of the column address signal CA.
FIG. 15 is a block diagram showing a configuration of a simplified cache system utilizing a page mode or a static column mode of the DRAM devices in FIGS. 12 to 14. FIG. 16 is a operation waveform diagram of the simplified cache system of FIG. 15.
In FIG. 15, a main memory 21 is formed to have capacity of 4M bytes by 8 DRAM devices 20 of 1M.times.4 bit structure. In this case, 20 (2.sup.20 =1048576=1M) address lines are required before a row address signal and a column address signal are multiplexed. However, the row address signal RA and the column address signal CA are multiplexed by an address multiplexer 22, so that 10 address lines are in fact connected to each DRAM device 20.
The operation of the simplified cache system of FIG. 15 will now be described with reference to the operation waveform diagram of FIG. 16.
An address generator 23 generates an address signal AD of 20 bits corresponding to the data required by a CPU 24. A latch (tag) 25 holds the row address signal corresponding to the data selected in the previous cycle. A comparator 26 compares the 10 bit row address signal RA among 20 bit address signals AD with the row address signal held in the latch 25. If those coincide with each other, it means the same row as that in the previous cycle has been accessed in the present cycle. This is called a "cache hit". In this case the comparator 26 generates a cache hit signal CH.
A state machine 27 is responsive to the cache hit signal CH to perform a page mode control in which the column address strobe signal CAS is toggled while maintaining the row address strobe signal RAS at a low level. At this time, the address multiplexer 22 applies a column address signal CA to each DRAM device 20 (see FIG. 16). As a result, data corresponding to the column address signal CA is outputted by way of the data group latched in the sense amplifier portion of each DRAM device 20. Thus, at the time of a cache hit, an output data, at a high speed, may be obtained from each DRAM device 20 at the access time t.sub.CAC.
If the row address signal RA generated from the address generator 23 and the row address signal held in the latch 25 do not coincide with each other, it means a row different from that of the previous cycle has been accessed in the present cycle. This is called a "cache miss".
In this case, the comparator 25 does not generate a cache hit signal CH. The state machine 27 performs an RAS/CAS control of the normal read cycle, and the address multiplexer 22 in turn applies the row address signal RA and the column address signal CA to each DRAM device 20 (see FIG. 16). Thus, at the time of a cache miss, a normal read cycle, which starts with a precharge by the row address strobe signal RAS, is initiated, and an output data, at a low speed, is obtained at the access time t.sub.RAC. Therefore, the state machine 27 generates a wait signal Wait to set the CPU 24 in a stand-by state. At the time of a cache miss, a new row address signal RA is held in the latch 25.
In the simplified cache system of FIG. 15, the data of one row of each array block in each DRAM device 20 (1024 bits in the case of 1M.times.4 bit DRAM device) is latched as one data block in the sense amplifier group. Accordingly, the size of one data block is unnecessarily large, so that the data blocks (the number of entries) held in the latch (tag) 25 become insufficient. For example, in the simplified cache system of FIG. 15, the number of entries is 1. Accordingly, there is a problem that the rate in which a cache hit occurs (cache hit rate) is low.